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CoaXPress Frame Grabber Series from Silicon Software Completed
Silicon Software GmbH Posted 05/03/2018
Mannheim (Germany)– Silicon Software GmbH, manufacturer of frame grabbers and intelligent image processing solutions, introduces two new members to its microEnable 5 marathon CXP family, the ACX-SP and ACX-DP that focus on the CoaXPress standard for demanding high-speed applications. All compatible CoaXPress camera types can be connected to the image acquisition and processing boards. They are suited for all CoaXPress configurations (CXP-1 to CXP-6) according to version 1.1.1.
The FPGA based microEnable 5 marathon frame grabber series has been developed for the Camera Link, Camera Link HS and CoaXPress cameras. Four CoaXPress boards are now part of the series: The A-Series, ACX-QP with four ports, ACX-DP with two ports and ACX-SP with one port as well as the programmable FPGA version VCX-QP (V-Series). The frame grabbers support color (RGB and Bayer) and monochrome area, line scan and CIS cameras across different topologies (single, dual and quad configurations) and up to 25 GB/s incoming bandwidth.
The new microEnable 5 marathon ACX-SP and ACX-DP frame grabbers consist of smaller versions with one or two camera ports for single link and dual link CXP cameras. They offer similar feature sets like the quad port frame grabber with an equally high bandwidth of 6.25 Gbit/s data rate per single CXP-6 connection.
The four ports of the microEnable 5 marathon ACX/VCX-QP frame grabbers can be connected to four different CoaXPress cameras at the same time with a multitude of pixel formats and bit depths. The VCX-QP version (V-Series) FPGA is graphically programmable with VisualApplets using data flow models. In a short period of time, developers create complex image processing pipelines for real-time, deterministic and low-latency applications. Existing FGPA hardware code (created with VHDL or Verilog) can also be integrated using VisualApplets Expert.
High data rates with lowest latencies
All four frame grabbers include FPGA-based image pre-processing (e.g. Bayer filter, lookup tables and white balance) at a very high frame rate, minimizing CPU load and accelerating the computer’s overall system performance. This guarantees a cost-efficient system setup with increased application performance. Based on PCI Express x4 (Gen 2) they take advantage of the DMA1800 technology, achieving the maximum data throughput 2.5 GB/s at 4-channel operation via data reduction with intelligent image pre-processing.
General Purpose Input/Output signals can be used for all four frame grabbers via two GPIO connections that are independently configurable (card edge GPIO and inboard GPIO with an interface to TTL or Opto trigger boards). With these trigger signals it is possible to internally synchronize several frame grabbers or peripheral devices in series (daisy chain), amongst other techniques.
Comprehensive software tools and the SDK support developers at the configuration and implementation of vision systems. With this, GenICam compatible cameras are identified automatically and their settings can be configured directly and saved via the user interface.
With these new frame grabbers, Silicon Software increases its focus on the CoaXPress standard, which is particularly suited for industrial multi-device and multi-camera solutions requiring high bandwidths, real-time image processing, deterministic performance, the lowest latencies and cabling up to 100 meters. Many new applications are possible in the industrial image processing, aviation and medical markets.