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Proce V:
PCIe x8 (Gen 3) FPGA Computation Accelerator Based on Altera Stratix V GX (A3, A7, AB)/GS (D5, D8) FPGAs in a Gen 3 PCIe x 8 Lanes Form Factor with up to 16GB DDR III

The ProceV system is based on Altera’s newest generation Stratix V FPGA device. The ProceV provides massive capacity (up to 952K LEs), and high memory and I/O performance. In addition to 8-Lane PCIe gen 3, twenty six 12.5/14.1 Gb/s transceivers provide external IOs of up to 366 Gb/s (full duplex). The combination of high-speed direct communication to the FPGA via PCIe, CXP, SFP+, and General Purpose high-speed transceivers makes the ProceV ideal for low-latency, high performance networking and HPC applications. Powerful memory scheme, composed of embedded memory with 8 TB/s throughput, 16 GB ECC DDR III and optional 288 Mb DDR II SRAM, enables high bandwidth computation and networking, and unique flexibility to achieve diverse algorithm architectures. Using an external clock, a GiDEL or user dedicated add-on daughter boards, the FPGA device can directly interface with standard protocols such as HDMI, SDI and Camera Link as well as with user's propriety IO systems. Eight-lane PCIe Gen. 3 interface allows for strong co-processing between a standard PC operating system and an FPGA based accelerator. The ProceV system conjoined with GiDEL's ProcDeveloper's Kit maximizes system performance while significantly improving development productivity. Based on this powerful development suite, for over 15 years GiDEL has consistently been able to meet unique costumer requirements while allowing for flexibility to accommodate long-term product evolution.

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